In data processing systems, a bus is commonly employed to interconnect various elements of the system. For example, a central processing unit (CPU) is typically connected to a memory unit (main memory) and input/output (I/O) devices via a bus capable of carrying the signals associated with the operation of each element. These signals include address and data signals, clock signals, and various control signals. The bus will ordinarily be capable of carrying such signals to all elements coupled to the bus so that the data processed by the system can be transferred among the various elements of the system.
As data processing systems achieve increasingly higher levels of performance, it is sometimes desirable to provide more than one bus in the system. For example, it may be desired to provide a high speed main system bus which interconnects multiple CPUs to a main memory, and to provide a separate I/O bus which interconnects the system bus with I/O devices such as disk drives, tape drives and network controllers.
To transfer signals between the separate buses in a multibus data processing system, the buses must be suitably interconnected. In general this requires a bus adapter that is connected to both buses and operates on each according to the characteristics of that bus. Specifically, when data is to be transferred from one device to another device on a bus, a transaction is initiated on that bus according to a predetermined set of rules, commonly called a protocol, which is specific to that bus. A transaction is generally defined as a complete logical task performed on a bus, involving one or more transfers of data.
The internal organization of the main memory is important to the performance of the multibus data processing system. The internal data path of the memory is typically designed to be consistent with the amount of data that can be transferred to and from a CPU in a single bus cycle, i.e. the width of the data path of the system bus. This amount, termed a block, is as large as feasible so as to maximize the overall efficiency of the data processing system by reducing the number of system bus and memory cycles needed to transfer data to and from main memory.
Although I/O devices typically transfer large amounts of data to and from main memory, the architecture of the I/O bus may limit the size of I/O data transfers to something less than the block transfer size of the memory and system bus. Therefore, the transfer of data between the I/O devices and main memory may be a factor that limits overall data processing system throughput and efficiency.
Previously, an adapter connected to the I/O bus on which a transaction is initiated would receive the data from the I/O bus, place the data into its internal buffer and then obtain control of the system bus by issuing a request signal on the system bus. The adapter would then gain control of the system bus in response to a grant signal and begin to generate the signals which constitute a write data operation on the system bus, the operation including the transfer of the data resident in the adapter's buffer.
If the transaction size of the data on the I/O bus is less than a main memory block, the adapter's write operation to main memory will result in an increase in the number of memory cycles required to transfer data into the memory. For example, a write operation to main memory of less than a block of data will result in a read-modify-write operation to modify the desired data and calculate the proper ECC code. That is, an entire block of data will be read from the memory's array, a selected portion of that data block will be modified, and then the full block will be written back to the memory location. Such an operation decreases the memory bandwidth, that is, it increases the time required per unit of data transferred into the main memory.
U.S. Pat. No. 4,878,166, issued Oct. 31, 1989 to Johnson et al. describes a method and apparatus for transferring data between a first bus or Local Bus, to which a first set of high performance devices is attached, and a second bus or Remote Bus, to which a second set of relatively lower performance devices is attached. The apparatus described therein includes transfer means coupled to pack/funneling means, such that all data to and from the transfer means and either an I/O port or DMA channel must pass through the packing/funneling means.
For data returned to the Local Bus (read operation), the data is "right adjusted" and "packed" by the packing/funneling means into a 32 bit word since all transfers on the Local Bus are 32 bits wide, while for data sent to the Remote Bus (write operation), the packing/funneling means "funnels" copies of the data bits juxtaposed in one word to the Remote Bus.
Therefore, in accordance with an aspect of the present invention, an object is to provide a new and improved method and apparatus for optimizing data transfers to and from I/O devices and main memory.
Additionally, an object of the present invention is to maximize system bus and memory bandwidth in a multibus data processing system.